1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to nonvolatile semiconductor memory devices and to methods of operating nonvolatile memory devices.
2. Description of the Related Art
The demand for electrically programmable and electrically erasable nonvolatile memory devices has increased dramatically in recent years. Such devices are at least partially characterized by the ability to maintain stored data even in the absence of supplied power. The use of so-called flash memories has become especially popular, particularly, but not exclusively, in the context of portable devices such as digital cameras, cell phones, personal data assistants (PDAs), and laptop computers. Flash memories, such as NAND-type flash memories, are capable of storing large amounts of data in a relatively small area.
As background discussion, the basic operating principles underlying flash memory cells and flash memory devices are presented below. However, it should be clearly understood that the discussion that follows is merely exemplary and does not in any way limit and/or define the scope of the present invention.
The operating principle of a flash memory cell will be described first with reference to FIGS. 1A through 1C. FIG. 1A illustrates a typical configuration in which a flash memory cell transistor is connected to word and bit lines of a memory device, FIG. 1B shows the circuit symbol of a flash memory cell transistor, and FIG. 1C shows the threshold voltage characteristics of a flash memory cell transistor.
Referring collectively to FIGS. 1A through 1C, a flash memory cell transistor includes a source region 4 and a drain region 5 located at the surface of a substrate 3. In this example, the substrate is P-type, and the source and drain regions 4 and 5 are N+-type. A gate structure is aligned over a channel region defined between the source and drain regions 4 and 5. The gate structure includes a floating gate 1 and a control gate 2. Although not shown, a tunneling dielectric layer is interposed between the floating gate 1 and the surface of the substrate P-sub, and another thin oxide layer (or control dielectric) is interposed between the floating gate 1 and the control gate 2. In the illustrated example, the drain voltage Vd is supplied from a bit line BL, the control gate voltage Vcg is supplied from a word line WL, and the source voltage Vs is connected to a reference potential such as ground.
The threshold voltage (or voltages) of the flash memory cell transistor defines its stored logic value. That is, in the example of a single-bit cell transistor, when the flash memory cell transistor is in its initial state (also called an “erased” state), the threshold voltage Vth is relatively low as shown in FIG. 1C. In this state, the cell transistor is designated to have a logic value “1”, which generally corresponds to the ON state of a conventional transistor device. On the other hand, when the cell transistor is in its “programmed” state (PGM), the threshold voltage Vth is relatively high. This high threshold voltage state is designated to have a logic value “0”, which generally corresponds to the OFF state of a conventional transistor device.
In order to change (program) the cell transistor from its initial state to its programmed state, a process known as Fowler-Nordheim (FN) tunneling is utilized. Briefly, a relatively large positive potential difference is created between the control gate 2 and the substrate P-sub, and excited electrons within the channel on the surface of the substrate are caused to be pushed through and trapped in the floating gate 1. These negatively charged electrons act as a barrier between the control gate 2 and channel on the substrate, thus increasing the threshold voltage of the cell transistor as represented in FIG. 1C. The cell transistor can be brought back to its initial state by forming a large negative potential difference between the control gate 2 and the substrate P-sub, whereby resultant FN tunneling draws the trapped electrons back across the thin oxide layer between the floating gate 1 and substrate, thus removing the electron barrier and decreasing the threshold voltage Vth.
Multi-bit (or multi-state) nonvolatile memories are characterized by utilizing each cell transistor to store two or more bits of data simultaneously. FIG. 2 is a diagram for explaining the operation of an exemplary two-bit nonvolatile cell memory. The threshold voltages Vth of the large numbers of flash cell transistors found in flash memory devices generally exhibit bell curve distributions. In the example of FIG. 2, the cell transistor can be set in any one of four (4) different threshold distributions, i.e., a first state, a second state, a third state and a fourth state. Any cell transistor having a threshold voltage within the distribution defined by one of these four states is assigned a corresponding two-bit logic value, for example, “11”, “10”, “00” and “01” as shown in FIG. 2. The particular bit assignments illustrated in FIG. 2 are known in the art as “gray-coding.”
As mentioned above, a cell transistor is said to be “programmed” when its threshold voltage is increased from its normally ON state (its erased state) to a threshold voltage of a higher state. In FIG. 2, the threshold voltage distribution to the far left of the diagram (“11”) is the erased state. In two-bit programming of the cell transistor, two successive programming operations are executed, namely, a least significant bit (LSB) program mode, and a most significant bit (MSB) program mode. Examples of these LSB and MSB program modes are described below with reference to FIGS. 3-5.
Note first that the cell transistor is initially in its erased state, and accordingly, its initial logic value is “11” (FIG. 2). In this example, if the LSB of the data to be stored is “0”, then a programming operation is executed to increase the threshold voltage of the cell transistor from the first state to the second state (FIG. 3). On the other hand, if the LSB of the data to be stored is “1”, no programming is executed during the LSB program mode. Note here that the cell transistor is either in the first state or the second state after the LSB program mode.
Next the MSB of the data to be stored dictates operations in the MSB program mode. FIG. 4 illustrates the case where gray-coding has been adopted. Regardless of whether the cell transistor is in the first state or the second state after the LSB program mode, no programming is executed in the MSB program mode if the MSB of the data to be stored is “1”. On the other hand, if the MSB of the data to be stored is “0”, then programming occurs which is dependent on whether the cell transistor is in the first state or the second state after the LSB program mode. This is shown by the dashed lines appearing in FIG. 4. If the MSB of the data to be stored is “0”, and if the cell transistor is in the first state after the LSB program mode, then programming is executed to bring the threshold voltage of the cell transistor from the first state to the fourth state. On the other hand, if the MSB of the data to be stored is “0”, and if the cell transistor is in the second state after the LSB program mode, then programming is executed to bring the threshold voltage of the cell transistor from the second state to the third state.
FIG. 5 is similar to FIG. 4, except that binary coding has been adopted. In this case, the first through fourth threshold voltage states designate two-bit values of “11”, “10”, “01” and “00”. Again, regardless of whether the cell transistor is in the first state or the second state after the LSB program mode, no programming is executed in the MSB mode if the MSB of the data to be stored is “1”. On the other hand, if the MSB of the data to be stored is “0”, then programming occurs which is dependent on whether the cell transistor is in the first state or the second state after the LSB program mode. This is shown by the dashed lines appearing in FIG. 5. If the MSB of the data to be stored is “0”, and if the cell transistor is in the first state after the LSB program mode, then programming is executed to bring the threshold voltage of the cell transistor from the first state to the third state. On the other hand, if the MSB of the data to be stored is “0”, and if the cell transistor is in the second state after the LSB program mode, then programming is executed to bring the threshold voltage of the cell transistor from the second state to the fourth state.
Reading of the multi-bit nonvolatile memory will be described next with reference to FIGS. 6 and 7. In particular, FIG. 6 illustrates the LSB read mode in which the logic value of the LSB of the stored data is determined. The LSB read mode involves a first LSB read operation and a conditional second LSB read operation. In the first LSB read operation, a first read voltage Vread1 is applied to the word line of cell transistor. If the cell transistor is turned ON as a result, then the cell transistor must be in the first state (“11”). If the cell transistor remains OFF, then a second LSB read operation is executed by applying a second read voltage Vread2 to the word line of the cell transistor. Here, if the cell transistor remains OFF during the second LSB read operation, the cell transistor must be in the fourth state (“01”). On the other hand, if the cell transistor turns ON during the second LSB read operation, then the LSB of the stored data is “0”, but the MSB of the stored data remains unknown.
In the case of gray-coding, the MSB of the stored data can be detected by a single read operation. This is illustrated in FIG. 7 where the read operation is conducted by applying the third read voltage Vread3 to the word line of the memory cell. If the cell transistor turns ON, the MSB of the stored data is “1”. If the cell transistor remains OFF, the MSB of the stored data is “0”.
As should be apparent from the above, detection of the multiple bits of a multi-bit nonvolatile memory is quite complex when compared to the detection of a single-bit nonvolatile memory. Numerous challenges are encountered when designing and developing the circuitry needed to both program and read the multiple bits from individual cell transistors.